Today's Systems on a Chip (SoC) have very high level of integration with multiple voltage regulators, voltage monitors, analog to digital and digital to analog converters, power on reset controllers and other systems which significantly increase the scope and complexity of manufacturing test coverage as well as the cost of testing.
During its lifetime, a digital system is tested and diagnosed on numerous occasions. For the system to perform its intended mission with high availability, testing and diagnosis must be quick and effective. A sensible way to ensure this is to specify test as one of the system functions—in other words, self-test.
Digital systems involve a hierarchy of parts: chips, boards, cabinets, and so on. At the highest level, which may include the entire system, the operation is controlled by software. Self-test is often implemented in software. While a purely software approach to self-test may suffice at the system level, it has several disadvantages. Such testing may have poor diagnostic resolution because it must test parts designed without specific testability considerations. In addition, a good software test can be very long, slow, and expensive to develop.
An attractive alternative is built-in self-test, (BIST) that is, self-test implemented in hardware.
The basic BIST architecture requires the addition of three hardware modules to a digital circuit: a pattern generator; a response analyzer; and a test controller.
Examples of pattern generators are a ROM with stored patterns, a counter, or a linear feedback shift register (LFSR). A typical response analyzer is a comparator with stored responses or a signature analyzer. The signature analyzer may be implemented in a number of ways known in the art, with the most common being a Multiple Input Shift Register (MISR).
A control module is usually required to activate the test and analyze the responses.